root/XilinxTools/xst.py

Descriptions = {'opt_mode': 'Optimization Criteria', 'lso': 'Library Search Order', 'use_carry_chain': 'Use Carry Chain', 'xsthdpdir': 'Work Directory', 'use_default_init': 'Optimize FFs without INIT value', 'lc': 'Combine single LUTs in 2-output LUTs', 'fsm_encoding': 'FSM Encoding Algorithm', 'ram_style': 'RAM Style', 'mux_extract': 'Mux Extraction', 'async_to_sync': 'Treat asynchronous set/reset as if synchronous', 'partition_nb_levels': 'Hierarchy levels to partition', 'case': 'Case', 'dsp_utilization_ratio': 'DSP48 Utilization Ratio', 'cross_clock_analysis': 'Cross Clock Analysis', 'iuc': 'Ignore User Constraints', 'bus_delimiter': 'Bus Delimiter', 'shreg_extract': 'Shift Register Extraction', 'safe_implementation': 'Safe Implementation', 'old_instance_names': 'Use old instance naming (from 8.2 on)', 'decoder_extract': 'Decoder Extraction', 'partition_max_nb': 'Partition Max Number', 'priority_extract': 'Priority Encoder Extraction', 'resource_sharing': 'Resource Sharing', 'iobuf': 'Add I/O Buffers', 'fsm_extract': 'FSM Extraction', 'p': 'Target Device', 'rtlview': 'Generate RTL Schematic', 'rom_extract': 'ROM Extraction', 'ifn': 'Input/Project File Name', 'signal_encoding': 'Signal Encoding Algorithm', 'move_first_stage': 'Move First Flip-Flop Stage', 'compileonly': 'Exit After Compilation', 'xor_collapse': 'XOR Collapsing', 'tmpdir': 'Temporary Directory', 'partition_keep': 'Preserve Existing Partitions', 'loop_iteration_limit': 'VHDL loop iteration limit', 'register_balancing': 'Register Balancing', 'use_dsp48': 'Map on DSP48', 'ofmt': 'Output File Format', 'generics': 'Force top generic parameters', 'netlist_hierarchy': 'Netlist Hierarchy', 'bufgce': 'BUFGCE Extraction', 'power': 'Power Optimization', 'equivalent_register_removal': 'Equivalent Register Removal', 'opt_level': 'Optimization Effort', 'hierarchy_separator': 'Hierarchy Separator', 'work_lib': 'Work Library', 'bram_map': 'Map Logic on BRAM', 'keep_hierarchy': 'Keep Hierarchy', 'shift_extract': 'Logical Shifter Extraction', 'move_last_stage': 'Move Last Flip-Flop Stage', 'auto_partitioning': 'Automatic Partitioning', 'tristate2logic': 'Tristate to logic', 'bram_utilization_ratio': 'BRAM Utilization Ratio', 'top': 'Top Level Block', 'hide_messages': 'Hide Messages', 'use_sync_reset': 'Usage of Synch Reset', 'edifngc': 'Generate EDIF (NDF) file', 'write_timing_constraints': 'Write Timing Constraints', 'define': 'Force verilog defines', 'use_clock_enable': 'Use Clock Enable', 'mux_style': 'Mux Style', 'read_cores': 'Read Cores', 'use_sync_set': 'Usage of Synch Set', 'partition_size': 'Partition Size', 'optimize_primitives': 'Optimize Instantiated Primitives', 'uc': 'Synthesis Constraint File', 'rom_style': 'ROM Style', 'register_duplication': 'Register Duplication', 'fsm_style': 'FSM Style', 'slice_packing': 'Slice Packing', 'ifmt': 'Input Format', 'mult_style': 'Multiplier Style', 'vlgpath': 'Verilog Search Paths', 'max_fanout': 'Max Fanout', 'bufr': 'Number of Regional Clock Buffers', 'auto_bram_packing': 'Auto BRAM Packing', 'ent': 'VHDL Top Level Block', 'recursion_iteration_limit': 'VHDL recursion iteration limit', 'glob_opt': 'Global Optimization Goal', 'bufg': 'Maximum Global Buffers', 'reduce_control_sets': 'Reduce Control Sets', 'vlgincdir': 'Verilog Include Directories', 'verilog2001': 'Verilog 2001', 'slice_utilization_ratio_maxmargin': 'Slice Utilization Ratio Delta', 'arch': 'VHDL Top Level Architecture', 'iob': 'Pack I/O Registers into IOBs', 'tristate2logic_pullup': 'Tristate to logic pullup Pterm', 'ram_extract': 'RAM Extraction', 'xsthdpini': 'HDL Library Mapping File (.ini file)', 'ofn': 'Output File Name', 'slice_utilization_ratio': 'Slice Utilization Ratio', 'vlgcase': 'Verilog Case Implementation Style', 'sd': 'Cores Search Directories'}

Options = {'opt_mode': ['AREA', 'SPEED'], 'lso': ['*'], 'use_carry_chain': ['YES', 'NO'], 'xsthdpdir': ['*'], 'use_default_init': ['YES', 'NO'], 'lc': ['off', 'area', 'auto'], 'fsm_encoding': ['Auto', 'One-Hot', 'Compact', 'Sequential', 'Gray', 'Johnson', 'Speed1', 'User'], 'ram_style': ['Auto', 'Distributed', 'Block', 'Pipe_Distributed', 'Pipe_Block', 'Block_Power1', 'Block_Power2'], 'mux_extract': ['YES', 'NO', 'FORCE'], 'async_to_sync': ['NO', 'YES'], 'partition_nb_levels': ['*'], 'case': ['upper', 'lower', 'maintain'], 'dsp_utilization_ratio': ['*'], 'cross_clock_analysis': ['YES', 'NO'], 'iuc': ['YES', 'NO'], 'bus_delimiter': ['<>', '[]', '{}', '()'], 'shreg_extract': ['YES', 'NO', 'RTL'], 'safe_implementation': ['YES', 'NO'], 'old_instance_names': ['0', '1'], 'decoder_extract': ['YES', 'NO'], 'partition_max_nb': ['*'], 'priority_extract': ['YES', 'NO', 'FORCE'], 'resource_sharing': ['YES', 'NO'], 'iobuf': ['YES', 'NO'], 'fsm_extract': ['YES', 'NO'], 'p': ['*'], 'rtlview': ['YES', 'NO', 'ONLY'], 'rom_extract': ['YES', 'NO'], 'ifn': ['*'], 'signal_encoding': ['Auto', 'One-Hot', 'User'], 'move_first_stage': ['YES', 'NO'], 'compileonly': ['YES', 'NO'], 'xor_collapse': ['YES', 'NO'], 'tmpdir': ['*'], 'partition_keep': ['YES', 'NO'], 'loop_iteration_limit': ['*'], 'register_balancing': ['YES', 'NO', 'Forward', 'Backward'], 'use_dsp48': ['yes', 'no', 'true', 'false', 'auto', 'advanced'], 'ofmt': ['NGC', 'NCD', 'ACX', 'NGD'], 'generics': ['*'], 'netlist_hierarchy': ['as_optimized', 'rebuilt'], 'bufgce': ['YES', 'NO'], 'power': ['yes', 'no', 'true', 'false'], 'equivalent_register_removal': ['YES', 'NO'], 'opt_level': ['1', '2'], 'hierarchy_separator': ['', '', '_'], 'work_lib': ['*'], 'bram_map': ['YES', 'NO'], 'keep_hierarchy': ['YES', 'NO', 'SOFT'], 'shift_extract': ['YES', 'NO'], 'move_last_stage': ['YES', 'NO'], 'auto_partitioning': ['YES', 'NO'], 'tristate2logic': ['YES', 'NO', 'AUTO'], 'bram_utilization_ratio': ['*'], 'top': ['*'], 'hide_messages': ['none', 'hdl_level', 'low_level', 'hdl_and_low_levels'], 'use_sync_reset': ['NO', 'AUTO', 'YES'], 'edifngc': ['YES', 'NO'], 'write_timing_constraints': ['YES', 'NO'], 'define': ['*'], 'use_clock_enable': ['NO', 'AUTO', 'YES'], 'mux_style': ['Auto', 'MUXF', 'MUXCY'], 'read_cores': ['YES', 'NO', 'OPTIMIZE'], 'use_sync_set': ['NO', 'AUTO', 'YES'], 'partition_size': ['*'], 'optimize_primitives': ['YES', 'NO'], 'uc': ['*'], 'rom_style': ['Auto', 'Distributed', 'Block'], 'register_duplication': ['YES', 'NO'], 'fsm_style': ['LUT', 'BRAM'], 'slice_packing': ['YES', 'NO'], 'ifmt': ['VHDL', 'Verilog', 'Mixed', 'Ngo', 'Ngd'], 'mult_style': ['block', 'lut', 'auto', 'pipe_lut', 'pipe_block'], 'vlgpath': ['*'], 'max_fanout': ['*'], 'bufr': ['*'], 'auto_bram_packing': ['YES', 'NO'], 'ent': ['*'], 'recursion_iteration_limit': ['*'], 'glob_opt': ['AllClockNets', 'Inpad_to_Outpad', 'Offset_in_before', 'Offset_out_after', 'Max_Delay'], 'bufg': ['*'], 'reduce_control_sets': ['auto', 'no'], 'vlgincdir': ['*'], 'verilog2001': ['YES', 'NO'], 'slice_utilization_ratio_maxmargin': ['*'], 'arch': ['*'], 'iob': ['true', 'false', 'auto'], 'tristate2logic_pullup': ['YES', 'NO'], 'ram_extract': ['YES', 'NO'], 'xsthdpini': ['*'], 'ofn': ['*'], 'slice_utilization_ratio': ['*'], 'vlgcase': ['Full', 'Parallel', 'Full-Parallel'], 'sd': ['*']}